*** CooCox/CoX ***
http://www.coocox.org/cox/manual/interface/index.html
What's CoX ?
CoX is the definition of a group of interface function. It defines the functional access functions of MCU's common peripherals, such as I2C, SPI, UART, etc.
CoX Peripheral Library can be divided into four parts:
Common mandatory type interface.
Common type of non-mandatory interface.
MCU-specific interface.
MCU register interface.
Features
Free and Open source under BSD license
Peripherals library with a unified standard interface, can be ported to other MCUs easily, Supports the platforms of ICCARM, ARMCC, GCC
Full functions of the peripheral, CoX still provides a set of APIs for special MCU features
Support interrupt, CoX extracts a set of interrupt events
A lot of reused drivers
Extensive documentation generated using doxygen standard
Standard definition of the API reference for almost all the Cortex-M0/M3 MCU manuals
Add a new innovative element, such as the short pin (PA2) in GPIO module
Strict coding standard and does not affect code size and speed, through rigorous testing and verification
Configurable
Provide blank template to make port more easily
Why do we use CoX ?
CoX Peripheral is not only a common interface for drivers, but also a full peripheral library.
CoX function interface unify the definition of the access functions of MCU's common peripherals, which makes you port programs among different MCUs more conveniently.
CoX has a set of specific realization for each MCU, and its code size and speed are nearly the same as the library that the suppliers provided.
When should we use CoX ?
If users may change MCU in the future and do not want to do too much unnecessary port work.
If users plan to use the existing drivers based on CoX interface.
The process of CoX evolution ?
CoX V1.0.0 was first released in September 2010, and has been ported to several MCU platforms, such as LPC11xx, NUC1xx and so on.
CoX V1.0.0 also provides a group of common functions for peripherals, but it has some drawbacks:
Do not support interrupt.
Does not have full functions. It just implements some of the most common functions, and can't play the advantages of the special MCUs.
Does not support all the peripherals, users need to rely on the cooperation of other libraries. That will also leads to larger code size, and may have some conflicts for logic implementation.
So we re-write the CoX. We have prepared for about one year for the new CoX, each of whose interface was defined after having read and compared a number of chip manufacturers'manuals. The current version of CoX has solved all the problems above, and added some innovative things. Now the CoX peripheral library can meet different needs, such as reusable driver, specified application and so on.
How to use CoX?
CoX is a group of APIs and Macros who have the prefix x. such as xGPIOPinRead(), etc.
Click here to see more about how to use CoX: How to.
CoX Peripheral Interfaces List and Roadmap
Interface Description State Date
Start-up Code CoX startup code
09/2011
LowLayer CoX lowlyaer support, such as type define, register define,
debug assert and so on.
09/2011
xCORE Cortex-M0/M3 Core Peripheral Interface
09/2011
SysCtl System Control(CG & PMC) Peripheral Interface
09/2011
DMA DMA Peripheral Interface
09/2011
GPIO GPIO & AFIO Peripheral Interface
09/2011
UART UART Peripheral Interface
09/2011
SPI SPI(SSI) Peripheral Interface
09/2011
I2C I2C Peripheral Interface
09/2011
TIMER Timer Peripheral Interface
09/2011
PWM PWM Peripheral Interface
09/2011
RTC RTC Peripheral Interface
09/2011
WDT Watchdog Timer Peripheral Interface
09/2011
ADC ADC Peripheral Interface
09/2011
ACMP Analog Comparator Peripheral Interface
09/2011
I2S Inter-Integrated Circuit Sound(I2S) Peripheral Interface
12/2011
CAN CAN Bus Peripheral Interface
12/2011
USB USB Device/Host/OTG Peripheral Interface
12/2011
EBI EBI bus Peripheral Interface
12/2011
CoX Support MCU List and Roadmap
Manufacturer Series State Date Download
CooCox CoX Port Template
09/2011 Download
Nuvoton NUC1xx
09/2011 Download
NUC122
11/2011 NA
M051
12/2011 NA
NXP LPC11c1x
2012 NA
LPC11xx
12/2011 NA
LPC12xx
2012 NA
LPC13xx
2012 NA
LPC17xx
2012 NA
ST STM32F10x
12/2011 NA
TI Stellaris
12/2011 NA
If you hope other MCUs can be supported by CoX as soon as possible, you can develop them by yourself with our guide, contact us please!
*** CoX Peripheral Interface V2.1 ***
http://www.coocox.org/cox/manual/interface/group___s_p_i.html#details
Collaboration diagram for SPI:
Modules
xSPI
CoX SPI Peripheral Interface.
Detailed Description
Serial Peripheral Interface (SPI) Peripheral Driver.
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction interface.
Configure the SPI controler as master device or a slave , it should generate clock and chip-select signal if it is set as master .
Each SPI controller can generates an individual interrupt when data transfer is finished and the respective interrupt event flag IF will be set. The interrupt event flag will generates an interrupt to CPU if the interrupt enable bit IE is set.
Transfer and receive data which is in your mode
2. SPI Function Description
2.1 SPI device controller configuration
Configure the SPI controller as a master or a slave device. It should generate clock and chip-select signals if it is set as a master device.
2.2 SPI interrupt control
Each SPI controller can generate an individual interrupt when data transfer is finished and the respective interrupt event flag IF will be set. The interrupt event flag will generates an interrupt to CPU if the interrupt enable bit IE is set.
2.3 SPI Transfer and Receive data
Transfer and receive data.
*** xSPI ***
http://www.coocox.org/cox/manual/interface/group__x_s_p_i.html#details
Collaboration diagram for xSPI:
Modules
xSPI Interrupts
Values that show xSPI interrupts
.
xSPI Interrupt Event
Values that show xSPI interrupt events.
.
xSPI Configure
Values that show xSPI Configure
.
xSPI DMA
Values that show xSPI DMA
.
xSPI Slave Select Mode
Values show xSPI Slave Select Mode
.
xSPI Slave Select
Values that show xSPI Slave Select
.
xSPI API
xSPI API Reference.
Detailed Description
CoX SPI Peripheral Interface.
The xSPI is the SPI Peripheral Interrupt of CoX. It defines some common macros and APIs macro and APIs
Contents
1 How is the SPI API Standard Define?
2 API Groups
2.1 2.1 SPI configuration control APIs
2.2 SPI Interrupt Control APIs
2.3 SPI Transfer&Receive Control
3 Program Examples
1 How is the SPI API Standard Define?
CoX SPI defines the APIs based on the following common functions:
SPI Configure Control
Master or Slave Select
Clock Mode and data width
SPI Interrupt control
Enable Interrupt
ISR and CallBack Function
SPI Transfer and Receive
Configure SPI as master or slave mode
Implement Transfer and Receive
2 API Groups
The CoX SPI APIs can be classified into three groups by functions:
those that deal with SPI mode configuration,
those that deal with SPI interrupt controlling,
those that deal with SPI transfer and receive control.
2.1 2.1 SPI configuration control APIs
xSPIConfigSet()
xSPIEnable()
xSPIDisable()
xSPIDMADisable()
xSPIDMAEnable()
2.2 SPI Interrupt Control APIs
xSPIIntEnable()
xSPIIntDisable()
xSPIIntStatusGet()
xSPIIntPendingClear()
2.3 SPI Transfer&Receive Control
xSPIDataWrite()
xSPIDataRead()
xSPIBitLengthGet()
xSPISingleDataReadWrite()
xSPIIsTxFull()
xSPIIsRxFull()
xSPIIsTxEmpty()
xSPIIsRxEmpty()
xSPIIsBusy()
3 Program Examples
The following example shows how to use the SPI APIs to configue SPI and to implement the function of transferring and receiving.
#include "xhw_memmap.h"
#include "Xspi.h"
#include "Xhw_spi.h"
#include "Xsysctl.h"
#include "xhw_types.h"
#include "Xgpio.h"
#include "Xhw_gpio.h"
#include "SPI_loop.h"
#include "Xhw_sysctl.h"
#include "test.h"
#include "testcase.h"
unsigned char SendData[] = "Wonderful World";
unsigned char ReceData[64];
unsigned long i;
//*****************************************************************************
//Ininite the SPI case which is needed
//param None
//This function ininite the SPI including clock source and enable spi
//return none
//*****************************************************************************
void SpiReceiveTransferInit(void)
{
SysCtlKeyAddrUnlock();
xHWREG(SYSCLK_PWRCON) |= SYSCLK_PWRCON_XTL12M_EN;
xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_OE;
xHWREG(SYSCLK_PLLCON) &= ~SYSCLK_PLLCON_PD;
//
// Set SysClk 36MHz using Extern 12M oscillator
//
xSysCtlClockSet(36000000, xSYSCTL_OSC_MAIN|xSYSCTL_XTAL_12MHZ);
//
// Enable Peripheral SPI0,SPI1
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI1);
SPIIntEnable(SPI0_BASE, TransferOver);
}
//*****************************************************************************
//Spi Master Slave Mode Configure
//param None
//This function configure the SPI as master and slave mode at the same time
//transfer and receive data
//return None
//*****************************************************************************
void SpiMasterSlaveModeConfig(void)
{
//
// Configure Some GPIO pins as SPI Mode
//
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_2);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_3);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_0);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_1);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_9);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_8);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_10);
GPIOPinFunctionSet(GPIO_FUNCTION_SPI, GPIO_PORTC_BASE,GPIO_PIN_11);
//
// Master Mode polarity 0,Rx latched at rising edge Tx changed at rising edge
// 2000000Hz 8Bits Data windth SPI MSB First
//
SPIConfig(SPI0_BASE,2000000,SPI_FORMAT_MODE_5|SPI_DATA_WIDTH8|SPI_MSB_FIRST|SPI_MODE_MASTER);
//
// Slave Mode polarity 0,Rx latched at rising edge Tx changed at rising edge
// 2000000Hz 8Bits Data windth SPI MSB First
//
xHWREG(SPI1_BASE + SPI_CNTRL) = 0x00000000;
xHWREG(SPI1_BASE + SPI_CNTRL) |= 0x00040844;
//
// Software Control Transfer Select SS0 and SS1
//
xSPISSSet(SPI0_BASE,xSPI_SS_SOFTWARE,SPI_SS0);
//
// Level Trig Slave at High Level
//
SPISSConfig(SPI0_BASE, SPI_SS_LEVEL_TRIGGER,SPI_SS_ACTIVE_HIGH_RISING);
SPISSConfig(SPI1_BASE, SPI_SS_LEVEL_TRIGGER,SPI_SS_ACTIVE_HIGH_RISING);
for(i=0;i<1;i++)
{
SPIDataWrite(SPI0_BASE,SendData,15);
SPIDataRead(SPI1_BASE,ReceData, 16);
TestIOPut('O');
TestIOPut('K');
}
TestIOPut('\n');
for(i=0;i<18;i++)
{
TestIOPut(ReceData[i]);
}
}
//******************************************************************************
//
// The main function of the SPI transfer
//
//******************************************************************************
int main(void)
{
SpiReceiveTransferInit();
SpiMasterSlaveModeConfig();
while(1)
{
}
}
.END
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