LPC1114 SPI reading notes

NXP Semiconductors LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller

Product data sheet - Rev. 8.1 — 24 May 2013

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Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package only).

7.9 SPI serial I/O controller

The LPC1100 and LPC1100L series contain two SPI controllers on the LQFP48 package and one SPI controller on the HVQFN33/TSSOP28/DIP28/TSSOP20/SO20 packages (SPI0).

The LPC1100XL series contain two SPI controllers.

Both SPI controllers support SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.9.1 Features

• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame



UM10398 LPC111x/LPC11Cxx User manual Rev. 12.1 — 7 August 2013

Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP

14.1 How to read this chapter

The SPI blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The second SPI block, SPI1, is available on LQFP48 packages.

For parts in the LPC1100 and LPC1100L series, SPI1 is not available on HVQFN33 packages.

For parts in the LPC1100XL series, SPI1 is supported on all packages.

Remark: Both SPI blocks include the full SSP feature set, and all register names use the SSP prefix.

14.2 Basic configuration

The SPI0/1 are configured using the following registers:

1. Pins: The SPI pins must be configured in the IOCONFIG register block. In addition, use the IOCON_LOC register (see Section 7.4) to select a location for the SCK0 function.

2. Power: In the SYSAHBCLKCTRL register, set bit 11 and bit 18 (Table 21).

3. Peripheral clock: Enable the SPI0/1 peripheral clock by writing to the SSP0/1CLKDIV registers (Section 3.5.15 and Section 3.5.17).

4. Reset: Before accessing the SPI blocks, ensure that the SSP_RST_N bits (bit 0 and bit 2) in the PRESETCTRL register (Table 9) is set to 1. This de-asserts the reset signal to the SPI blocks.

14.3 Features

• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.

• Synchronous Serial Communication.

• Supports master or slave operation.

• Eight-frame FIFOs for both transmit and receive.

• 4-bit to 16-bit frame.

14.4 General description

The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice it is often the case that only one of these data flows carries meaningful data.

The LPC111x/LPC11Cxx has two SPI/Synchronous Serial Port controllers.

SCK0/1 I/O SCK CLK SK Serial Clock.

SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When SPI/SSP interface is used, the clock is
programmable to be active-high or active-low, otherwise it is always active-high. SCK only switches during a data transfer. Any other time, the SPI/SSP interface either holds it in its inactive state or does not drive it (leaves it in high-impedance state).

SSEL0/1 I/O SSEL FS CS Frame Sync/Slave Select.

When the SPI/SSP interface is a bus master, it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent.The active state of this signal can be high or low depending upon the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal qualifies the presence of data from the Master according to the protocol in use.

When there is just one bus master and one bus slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s corresponding input. When there is more than one
slave on the bus, further qualification of their Frame Select/Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer.

MISO0/1 I/O MISO DR(M) DX(S) SI(M) SO(S)

Master In Slave Out. The MISO signal transfers serial data from the slave to the master. When the
SPI/SSP is a slave, serial data is output on this signal. When the SPI/SSP is a master, it clocks in
serial data from this signal. When the SPI/SSP is a slave and is not selected by FS/SSEL, it does not
drive this signal (leaves it in high-impedance state).

MOSI0/1 I/O MOSI DX(M) DR(S) SO(M) SI(S)

Master Out Slave In. The MOSI signal transfers serial data from the master to the slave. When the
SPI/SSP is a master, it outputs serial data on this signal. When the SPI/SSP is a slave, it clocks in
serial data from this signal.

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