MCP3208 MOSI test waveform

MCP3208 MOSI waveform

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void mcp320801()
{
// Setup transfer buffers ***
#define BUFFER_SIZE 0x03
uint8_t Tx_Buf[BUFFER_SIZE];
uint8_t Rx_Buf[BUFFER_SIZE];

    // Setup SPI0 with clock pin P06
setUpSpi050(SCK0_PIO0_6);

// Setup SSEL0 with P02
setupSpiSsel();

    // Setup xfer data configuration struct
    SSP_DATA_SETUP_Type xferConfig;
    xferConfig.tx_data = Tx_Buf;
    xferConfig.rx_data = Rx_Buf;
    xferConfig.length = BUFFER_SIZE;

    // Initialize MCP3208 Tx and Rx buffers

#define SINGLE_END_MODE 0x06; // bit 1 = 1
#define DIFFERENTIAL_END_MODE 0x04; // bit 1 = 0

    uint8_t channelNumber;
    uint8_t inputMode;

    channelNumber = 7;
    inputMode = SINGLE_END_MODE;

    Tx_Buf[0] = inputMode | (channelNumber >> 2);
    Tx_Buf[1] = channelNumber << 0x6;
    Tx_Buf[2] = 0x00; // Don't care

Rx_Buf[0] = 0x00;
Rx_Buf[1] = 0x00;
Rx_Buf[2] = 0x00;

    uint8_t j;
    for (j = 0; j < 10000000; j++)
    {
    delayMilliSecond(1);
    setSselLow();
        SSP_ReadWrite(LPC_SSP0, &xferConfig, SSP_TRANSFER_POLLING);
        setSselHigh();
    }
}

void setUpSpi050(SCK0_Position_Typedef sck0)
{
// Enable SSP0 block clock
SYSCON_AHBPeriphClockCmd(SYSCON_AHBPeriph_SSP0, ENABLE);

// Reset SSP0 and clock divider
SYSCON_PeriphResetCmd(SYSCON_RSTPeriph_SSP0, ENABLE);
SYSCON_PeriphResetCmd(SYSCON_RSTPeriph_SSP0, DISABLE);
SYSCON_SetSPI0ClockDiv(10);

// Assign GPIO pins for SPI
// SSP_SSP0PinsInit(sck0, ENABLE);
SSP_SSP0PinsInit(sck0, DISABLE); // Disable SSEL

// Initialize SSP with default configuration (Master mode, 8 bit data)
SSP_CFG_Type SSP_ConfigStruct;
SSP_ConfigStructInit(&SSP_ConfigStruct);
SSP_Init(LPC_SSP0, &SSP_ConfigStruct);

// Enable SSP peripheral
SSP_Cmd(LPC_SSP0, ENABLE);
}

void setupSpiSsel()
{
setupGpioPinOutputLow050(PortPinArraySsel); // setup GPIO pin as output
}

void setSselLow()
{
setGpioDataPinLow01(PortPinArraySsel); // SSEL low
}

void setSselHigh()
{
setGpioDataPinHigh01(PortPinArraySsel); // SSEL low
}

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